This invention relates to the testing of integrated circuits, and more particularly to the testing of very large scale integration (VLSI) integrated circuits. Specifically, this invention relates to the testing of complementary metal oxide semiconductor (CMOS) VLSI chips after they have been packaged in a semiconductor package.
Testing a packaged integrated circuit chip requires that three types of tests be performed; functional test, delay test and DC parametric test.
Functional test consists of applying a predetermined pattern of logical ones and zeros on the input pins of the package, applying a clock pulse, if necessary, on the clock input pin, and reading the chip's response on the output pins of the package. The response will be a pattern of logical ones and zeros which can be compared to the expected result to determine if the chip functioned properly. In general, attempts are made to generate enough tests to test all of the functional circuitry of the chip.
Delay testing consists of applying pulses, or logical transitions, of very fast rise times on selected input pins and measuring the time required for the response to appear at the output. Since the number of circuits in the path through the chip is known, the average circuit delay can be calculated. Typically, enough different paths are delay tested to give a high confidence that all the circuits on the chip will operate at the required speed.
DC parametric testing consists of measuring the electrical parameters of the chip's circuits connected to the input and output (I/O) pins. This is done by forcing a voltage or a current into an I/O pin, depending upon whether the I/O pin is an input or an output, respectively, and measuring the current or voltage, respectively, at the I/O pin.
Testers to perform the tests described above have been in use for years. The general concept is a connection between each signal pin on the chip package and the tester. The tester connections to the chip pins are typically bi-directional so that they can be used to test either an input or output pin on the chip. The tester controller, quite often a programmable computer, controls the operation of the tester. Transfers between the tester and the device under test (DUT) during functional tests are performed in a broadside manner. That is, all of the input pins of the DUT receive a test signal at the same time, and all the outputs of the DUT are read at the same time. Therefore, the tester controller has to load the correct input test pattern into the correct latches corresponding to the chip's input pins prior to the broadside load and read the data from the correct latches corresponding to the chip's output pins.
As integrated circuit technology has progressed to what is now called VLSI, the number of I/O pins necessary on a chip to allow use of the added circuitry, has increased also. Integrated circuit packages with up to 256 pins may now be used to package VLSI chips, and this has caused VLSI testers to become very large and very expensive.
As circuit densities have increased, special attention must be given to the testability of the chip. One approach to provide testability has been to design chips such that all the internal registers can be connected together as a shift register. This concept, disclosed in copending patent application Ser. No. 332,866, filed 12-21-81, now abandoned, assigned to a common assignee, allows a tester to shift data into the internal registers for use during test. This concept greatly speeds up functional testing since it allows the tester to set conditions within the chip as well as at the input pins and makes each test independent of the previous test. Previous testers could not take advantage of this feature since they perform a parallel load instead of a serial shift of data.
Connectors on the testers typically use "pogo-pin" contacts. These are spring-loaded, telescoping, contacts with a pointed or cupped end, arranged in the same pattern as the pins on the DUT. When the DUT is aligned over the connector, a small force is applied to partially compress the pogo-pins. The spring within the pogo-pin resists this force and causes the pogo-pin to make contact with the pin on the DUT. Pogo-pins are easily damaged and or contaminated, and quite often will remain depressed. This causes either no connection or intermittent connection on subsequent tests.